RF transmitter with stable on-chip PLL

ABSTRACT

A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.

CROSS REFERENCE TO RELATED PATENTS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC

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BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention relates generally to wireless communication systems andmore particularly to an radio frequency transmitter.

2. Description of Related Art

Communication systems are known to support wireless and wire linedcommunications between wireless and/or wire lined communication devices.Such communication systems range from national and/or internationalcellular telephone systems to the Internet to point-to-point in-homewireless networks. Each type of communication system is constructed, andhence operates, in accordance with one or more communication standards.For instance, wireless communication systems may operate in accordancewith one or more standards including, but not limited to, IEEE 802.11,Bluetooth, advanced mobile phone services (AMPS), digital AMPS, globalsystem for mobile communications (GSM), code division multiple access(CDMA), local multi-point distribution systems (LMDS),multi-channel-multi-point distribution systems (MMDS), radio frequencyidentification (RFID), Enhanced Data rates for GSM Evolution (EDGE),General Packet Radio Service (GPRS), and/or variations thereof.

Depending on the type of wireless communication system, a wirelesscommunication device, such as a cellular telephone, two-way radio,personal digital assistant (PDA), personal computer (PC), laptopcomputer, home entertainment equipment, RFID reader, RFID tag, et ceteracommunicates directly or indirectly with other wireless communicationdevices. For direct communications (also known as point-to-pointcommunications), the participating wireless communication devices tunetheir receivers and transmitters to the same channel or channels (e.g.,one of the plurality of radio frequency (RF) carriers of the wirelesscommunication system or a particular RF frequency for some systems) andcommunicate over that channel(s). For indirect wireless communications,each wireless communication device communicates directly with anassociated base station (e.g., for cellular services) and/or anassociated access point (e.g., for an in-home or in-building wirelessnetwork) via an assigned channel. To complete a communication connectionbetween the wireless communication devices, the associated base stationsand/or associated access points communicate with each other directly,via a system controller, via the public switch telephone network, viathe Internet, and/or via some other wide area network.

For each wireless communication device to participate in wirelesscommunications, it includes a built-in radio transceiver (i.e., receiverand transmitter) or is coupled to an associated radio transceiver (e.g.,a station for in-home and/or in-building wireless communicationnetworks, RF modem, etc.). As is known, the receiver is coupled to anantenna and includes a low noise amplifier, one or more intermediatefrequency stages, a filtering stage, and a data recovery stage. The lownoise amplifier receives inbound RF signals via the antenna andamplifies then. The one or more intermediate frequency stages mix theamplified RF signals with one or more local oscillations to convert theamplified RF signal into baseband signals or intermediate frequency (IF)signals. The filtering stage filters the baseband signals or the IFsignals to attenuate unwanted out of band signals to produce filteredsignals. The data recovery stage recovers raw data from the filteredsignals in accordance with the particular wireless communicationstandard.

As is also known, the transmitter includes a data modulation stage, oneor more intermediate frequency stages, and a power amplifier. The datamodulation stage converts raw data into baseband signals in accordancewith a particular wireless communication standard. The one or moreintermediate frequency stages mix the baseband signals with one or morelocal oscillations to produce RF signals. The power amplifier amplifiesthe RF signals prior to transmission via an antenna.

While transmitters generally include a data modulation stage, one ormore IF stages, and a power amplifier, the particular implementation ofthese elements is dependent upon the data modulation scheme of thestandard being supported by the transceiver. For example, if thebaseband modulation scheme is Gaussian Minimum Shift Keying (GMSK), thedata modulation stage functions to convert digital words into quadraturemodulation symbols, which have a constant amplitude and varying phases.The IF stage includes a phase locked loop (PLL) that generates anoscillation at a desired RF frequency, which is modulated based on thevarying phases produced by the data modulation stage. The phasemodulated RF signal is then amplified by the power amplifier inaccordance with a transmit power level setting to produce a phasemodulated RF signal.

As another example, if the data modulation scheme is 8-PSK (phase shiftkeying), the data modulation stage functions to convert digital wordsinto symbols having varying amplitudes and varying phases (i.e., polarcoordinates). The IF stage includes a phase locked loop (PLL) thatgenerates an oscillation at a desired RF frequency, which is modulatedbased on the varying phases produced by the data modulation stage. Thephase modulated RF signal is then amplified by the power amplifier inaccordance with the varying amplitudes to produce a phase and amplitudemodulated RF signal.

As yet another example, if the data modulation scheme is x-QAM (16, 64,128, 256 quadrature amplitude modulation), the data modulation stagefunctions to convert digital words into Cartesian coordinate symbols(e.g., having an in-phase signal component and a quadrature signalcomponent) or polar coordinates. The IF stage includes mixers that mixthe in-phase signal component with an in-phase local oscillation and mixthe quadrature signal component with a quadrature local oscillation toproduce two mixed signals. The mixed signals are summed together andfiltered to produce an RF signal that is subsequently amplified by apower amplifier.

In each of the above described transmitters, a phase locked loop (PLL)is used to facilitate the generation of an RF signal. Typically, the PLLis fabricated on-chip with at least a part of the transmitter. An issuewith on-chip PLLs is maintaining the PLL's bandwidth at a desired level.Since the bandwidth of the PLL substantially influences the overallbandwidth of the transmitter, many techniques have been developed tocontrol the PLL's bandwidth. For example, one solution is to use anoff-chip loop filter circuit such that high precision components may beused. This has the obvious drawback of using an off-chip loop filter.Another solution is to use metal capacitors within an on-chip loopfilter, but metal capacitors are very large in comparison totransistors. Yet another solution is to calibrate the resistors andcapacitors within the loop filter. This solution requires an RC(resistor calibration circuit) that calibrates both the resistors andcapacitors. In some PLLs, the required operating frequency and bandwidthrequires such small resistors, it is impractical to calibrate them.

Therefore, a need exists for a phase locked loop that includes a loopfilter that overcomes at least some of the above mentioned limitationsfor use in RF transmitters and other applications.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theDrawings, the Detailed Description of the Invention, and the claims.Other features and advantages of the present invention will becomeapparent from the following detailed description of the invention madewith reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a schematic block diagram of an embodiment of a wirelesscommunication system in accordance with the present invention;

FIG. 2 is a schematic block diagram of an embodiment of a wirelesscommunication device in accordance with the present invention;

FIG. 3 is a schematic block diagram of another embodiment of a wirelesscommunication device in accordance with the present invention;

FIG. 4 is a schematic block diagram of an embodiment of an RFtransmitter in accordance with the present invention;

FIG. 5 is a schematic block diagram of another embodiment of an RFtransmitter in accordance with the present invention;

FIG. 6 is a schematic block diagram of another embodiment of an RFtransmitter in accordance with the present invention;

FIG. 7 is a schematic block diagram of an embodiment of a loop filter inaccordance with the present invention;

FIG. 8 is a schematic block diagram of an embodiment of a zero circuitin accordance with the present invention;

FIG. 9 is a schematic block diagram of an embodiment of a PLL inaccordance with the present invention; and

FIG. 10 is a schematic block diagram of another embodiment of a loopfilter in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram illustrating a communication system10 that includes a plurality of base stations and/or access points 12,16, a plurality of wireless communication devices 18-32 and a networkhardware component 34. Note that the network hardware 34, which may be arouter, switch, bridge, modem, system controller, et cetera provides awide area network connection 42 for the communication system 10. Furthernote that the wireless communication devices 18-32 may be laptop hostcomputers 18 and 26, personal digital assistant hosts 20 and 30,personal computer hosts 24 and 32 and/or cellular telephone hosts 22 and28. The details of the wireless communication devices will be describedin greater detail with reference to one or more of FIGS. 2-10.

Wireless communication devices 22, 23, and 24 are located within anindependent basic service set (IBSS) area and communicate directly(i.e., point to point). In this configuration, these devices 22, 23, and24 may only communicate with each other. To communicate with otherwireless communication devices within the system 10 or to communicateoutside of the system 10, the devices 22, 23, and/or 24 need toaffiliate with one of the base stations or access points 12 or 16.

The base stations or access points 12, 16 are located within basicservice set (BSS) areas 11 and 13, respectively, and are operablycoupled to the network hardware 34 via local area network connections36, 38. Such a connection provides the base station or access point 1216 with connectivity to other devices within the system 10 and providesconnectivity to other networks via the WAN connection 42. To communicatewith the wireless communication devices within its BSS 11 or 13, each ofthe base stations or access points 12-16 has an associated antenna orantenna array. For instance, base station or access point 12 wirelesslycommunicates with wireless communication devices 18 and 20 while basestation or access point 16 wirelessly communicates with wirelesscommunication devices 26-32. Typically, the wireless communicationdevices register with a particular base station or access point 12, 16to receive services from the communication system 10.

Typically, base stations are used for cellular telephone systems (e.g.,advanced mobile phone services (AMPS), digital AMPS, global system formobile communications (GSM), code division multiple access (CDMA), localmulti-point distribution systems (LMDS), multi-channel-multi-pointdistribution systems (MMDS), Enhanced Data rates for GSM Evolution(EDGE), General Packet Radio Service (GPRS), high-speed downlink packetaccess (HSDPA), high-speed uplink packet access (HSUPA and/or variationsthereof) and like-type systems, while access points are used for in-homeor in-building wireless networks (e.g., IEEE 802.11, Bluetooth, ZigBee,any other type of radio frequency based network protocol and/orvariations thereof). Regardless of the particular type of communicationsystem, each wireless communication device includes a built-in radioand/or is coupled to a radio.

FIG. 2 is a schematic block diagram of another embodiment of a wirelesscommunication system that includes a communication device 50 associatedwith a cellular network, a wireless local area network (WLAN) and/or awireless personal area network (WPAN) 58. The WLAN network is shown toinclude an access point 54, a local area network (LAN) bus 62, a modem70, a video source 72, an audio source 74, a printer 68, a personalcomputer (PC) 76, a facsimile machine (fax) 64, and a server 66, but mayinclude more or less components than shown. The cellular network isshown to include a base station 56, which may support voicecommunications and/or data communications. Note that the cellularnetwork may include more components than the base station 56. The WPAN58 includes at least one WPAN device 60 that is proximal to thecommunication device 50. Note that the WPAN device 60 may be a Bluetoothheadset, a wireless microphone, a wireless speaker, a wireless display,and/or a wireless data entry unit.

In this embodiment, the communication device 50, which may be one of thecommunication devices 18-32 of FIG. 1 or another type of communicationdevice, includes an integrated circuit (IC) 52 to communication with thecellular network, the WLAN, and/or the WPAN. Such a communication mayinclude voice communications, audio communications, videocommunications, graphics communications, text communications, and/ordata communications (e.g., emails, web browsing, short message services,etc.). For example, the communication device 50 may be receiving anaudio file from the audio source 74 (e.g., a computer storing an MP3file, a radio receiver, a cable set top box, a satellite receiver, a CDplayer, etc.), the server 66, and/or the PC 76 via the access point 54as an inbound RF wireless network (WN) data signal 78. The IC 52processes the inbound RF WN data signal 78 to produce inbound data thatmay be rendered audible by speaker circuitry of the IC 52 and/orcommunication device 50. Alternatively and/or in addition to, the IC 52may convert the inbound data signal from the WLAN to an outbound RF WNdata signal 80 that is provided to the WPAN device 60, which mayreproduce the inbound data for presentation (e.g., render it audible).

As another example, the communication device 50 may be receiving a videofile from the video source 72 (e.g., a computer storing a video file, acable set top box, a satellite receiver, a DVDD player, etc.), theserver 66, and/or the PC 76 via the access point 54 as an inbound RF WNdata signal 78. The IC 52 processes the inbound RF WN data signal 78 toproduce inbound data that may be presented on a display (e.g., speakersand LCD, DLP, or plasma display panel) of the communication device 50.Alternatively and/or in addition to, the IC 52 may convert the inbounddata signal from the WLAN to an outbound RF WN data signal 80 that isprovided to the WPAN device 60, which may reproduce the inbound data forpresentation (e.g., play the video file).

As yet another example, the communication device 50 may record video,voice, and/or audio to produce a recorded file. In this example, the IC52 may convert the recorded file into an outbound RF WN data signal 80that is provided to the WLAN. The access point 54 recovers the recordedfile and provides it to one of the other devices (e.g., PC 76, server66, modem 70) for storage and/or forwarding onto the Internet.

As a further example, the modem 70, the PC 76, the server 66, the fax64, and/or the printer 68 may provide a file to the access point 54 forcommunication to the communication device 50. In this instance, theaccess point 54 converts the file into the inbound WN data signal 78.The IC 52 processes the received the inbound WN data signal 78 torecapture the file, which may be presented on the communication device50 and/or provided to the WPAN device 60.

As yet a further example, the communication device 50 may have agraphics, text, and/or a data file for communication to a component ofthe WLAN. In this example, the IC 52 converts the graphics, text, and/ordata file into the outbound RF WN data signal 80 that is provided to theaccess point 54 and/or to the WPAN 60. In one embodiment, the accesspoint 54 recovers the graphics, text, and/or data file and provides itto the PC 76, the modem 70, the fax 64, the printer 68, and/or theserver 66. Note that the file may include an address that identifieswhich component(s) of the WLAN are to receive the file.

More examples include voice and/or data communications between thecommunication device 50 and the base station 56 in accordance with oneor more cellular communication standards, which includes, but is notlimited to, past, present, and/or future versions of GSM, CDMA, widebandCDMA (WCDMA), EDGE, GPRS, AMPS, and digital AMPS. For instance, the IC52 may process outbound voice signals to produce outbound RF voicesignals 88 and process inbound RF voice signals 84 to produce inboundvoice signals. The IC 52 may facilitate the presentation of the inboundand outbound voice signals on the communication device 50 and/ortransceive them with the WPAN device 60 as the inbound and outbound WNdata signals 78 and 80. Further the IC 52 may process outbound datasignals to produce outbound RF data signals 86 and process inbound RFdata signals 82 to produce inbound data signals. The IC 52 mayfacilitate the presentation of the inbound and outbound data signals onthe communication device 50 and/or transceive them with the WPAN device60 as the inbound and outbound WN data signals 78 and 80.

FIG. 3 is a schematic block diagram of another embodiment of a wirelesscommunication device that includes a baseband processing module 90 andan antenna structure 98 coupled to the IC 52. The IC 52 includes an RFtransmitter section 92, an RF receiver section 94, and an antennacoupling module 96. In another embodiment, the baseband processingmodule 90 may be included on the IC 52. In yet another embodiment, theantenna coupling module 96 may be off-chip (i.e., not on IC 52).

The baseband processing module 90 may be a single processing device or aplurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element, which may be a single memory device, aplurality of memory devices, and/or embedded circuitry of the processingmodule. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, cache memory, and/or any device that storesdigital information. Note that when the processing module implements oneor more of its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory and/or memory elementstoring the corresponding operational instructions may be embeddedwithin, or external to, the circuitry comprising the state machine,analog circuitry, digital circuitry, and/or logic circuitry. Furthernote that, the memory element stores, and the processing moduleexecutes, hard coded and/or operational instructions corresponding to atleast some of the steps and/or functions illustrated in FIGS. 3-10.

In operation, the baseband processing module 90 converts outbound data100 (e.g., voice, text messages, audio files, video files, image files,graphics, etc.) into an outbound symbol stream 102 in accordance withone or more wireless communication protocols (e.g., past, present,and/or future versions of GSM, CDMA, wideband CDMA (WCDMA), EDGE, GPRS,AMPS, digital AMPS, IEEE 802.11, Bluetooth, ZigBee, and/or any othertype of wireless network protocol). The outbound symbol stream 102 mayinclude in-phase and quadrature components, phase modulation component,amplitude modulation component, and/or a frequency modulation component.

The RF transmitter section 94, embodiments of which will be described ingreater detail with reference to FIGS. 4-6, converts the outbound symbolstream 102 into an outbound RF signal 104. The antenna coupling module96 (which may include a transformer balun, an impedance matchingcircuit, and/or a transmission line) provides the outbound RF signal 104to the antenna structure 98 for transmission. The antenna structure 98includes one or more antennas to transmit the outbound RF signal 104 andto receive an inbound RF signal 106.

The antenna coupling module 96 provides the inbound RF signal 106 to theRF receiver section 94. The RF receiver section 94, which includes a lownoise amplifier module, a down conversion mixing module, filtering,and/or an analog to digital converter, converts the inbound RF signal106 into an inbound symbol stream 108. The baseband processing module 90converts the inbound symbol stream 108 into inbound data 110 inaccordance with the one or more wireless communication protocols.

FIG. 4 is a schematic block diagram of an embodiment of an RFtransmitter 92 that includes a phase locked loop (PLL) 122, an off-chipcalibration resistor 138, and an amplifier module 122. The PLL 120includes a phase detector 124, a charge pump 126, a loop filter 128, acontrolled oscillator 130, and a feedback divider 132. The loop filter128 includes a zero circuit 136 and a pole circuit 134. The amplifiermodule 122 may include one or more power amplifier drivers and/or one ormore power amplifiers coupled in series and/or in parallel. Theamplifier module 122 may further include an amplitude modulation module.

In this embodiment, the phase detector 124 produces a difference signalbased on a difference between phase of a reference oscillation 140 andphase of a feedback oscillation provided by the feedback divider 132.The charge pump 126 converts the difference signal into an up-signal ora down signal. The loop filter 128 filters the up signal or the downsignal to produce a control signal and provides a wide and stablebandwidth (e.g., for GSM/EDGE communications, the PLL bandwidth is setwithin a range of 200-250 KHz).

To accomplish this, the loop filter includes the pole circuit 134 andthe zero circuit 136. The pole circuit 134 includes at least oneresistor and at least one capacitor and the zero circuit 136 includes atleast one resistor and at least one metal oxide semiconductor (MOS)capacitor to provide a desired frequency response for the PLL. Theoff-chip calibration resistor may be indirectly coupled to zero circuitand is used to calibrate the zero circuit 136. Various embodiments ofthe loop filter 128 and the compensation of the zero circuit 136 will bedescribed in greater detail with reference to FIGS. 7 and 8.

Continuing with the discussion of the operation of the PLL 120, thecontrolled oscillator 130, which may be a current controlled oscillatoror a voltage controlled oscillator, generates an output oscillationbased on the control signal. The feedback divider generates the feedbackoscillation from the output oscillation based on a divider value.

The amplifier module 122 amplifies the output oscillation to produce theoutbound RF signal 104. In this embodiment, the amplifier module 122further includes the amplitude modulation module, which converts atleast a portion of the outbound symbol stream 102 into amplitudemodulation information 142. The amplifier module 122 modulates theoutput oscillation in accordance with the amplitude modulationinformation 142 to produce the outbound RF signal 104. The amplitudemodulation information may be in accordance with amplitude modulation(AM), amplitude shift keying (ASK), m-bit quadrature amplitudemodulation (m-QAM) 8-bit phase shift keying (8-PSK) and/or any othermodulation scheme that varies the amplitude of the transmitted signal.

FIG. 5 is a schematic block diagram of another embodiment of an RFtransmitter that includes the phase locked loop (PLL) 122, the off-chipcalibration resistor 138, and the amplifier module 122. The PLL 120includes the phase detector 124, the charge pump 126, the loop filter128, the controlled oscillator 130, and the feedback divider 132. Theloop filter 128 includes the zero circuit 136 and the pole circuit 134.The feedback divider 132 includes a phase modulation (PM) section 144.

The phase modulation section 144, which may include a sigma deltamodulator coupled to a divider block of the feedback divider, receivesphase modulation information 146 of the outbound symbol stream 102. Thephase modulation section 144, in accordance with the phase modulationinformation 146, introduces a phase modulation into the feedbackoscillation. In this manner, the resulting output oscillation includesthe phase modulation. Note that the phase modulation information may bebased on binary phase shift keying (BPSK), quadrature PSK, m-bitquadrature amplitude modulation (m-QAM) 8-bit phase shift keying (8-PSK)and/or any other modulation scheme that varies the phase of thetransmitted signal.

The amplifier module 122 amplifies the phase modulated outputoscillation to produce the outbound RF signal 104. If the outboundsymbol stream 102 includes amplitude modulation information 142, theamplifier module 122 modulates the phase modulated output oscillation inaccordance with the amplitude modulation information 142 to produce theoutbound RF signal 104.

FIG. 6 is a schematic block diagram of another embodiment of an RFtransmitter that includes the phase locked loop (PLL) 122, the off-chipcalibration resistor 138, and the amplifier module 122. The PLL 120includes the phase detector 124, the charge pump 126, the loop filter128, the controlled oscillator 130, and the feedback divider 132. Theloop filter 128 includes the zero circuit 136 and the pole circuit 134.The feedback divider 132 includes a frequency modulation (FM) section145.

The frequency modulation section 145, which may include a sigma deltamodulator coupled to a divider block of the feedback divider, receivesfrequency modulation information 147 of the outbound symbol stream 102.The frequency modulation section 145, in accordance with the frequencymodulation information 147, introduces a frequency modulation into thefeedback oscillation. In this manner, the resulting output oscillationincludes the frequency modulation. Note that the frequency modulationinformation may be based on frequency modulation (FM), frequency shiftkeying (FSK), minimum shift keying (MSK), Gaussian MSK, Gaussian FSK,and/or any other modulation scheme that varies the frequency of thetransmitted signal.

The amplifier module 122 amplifies the frequency modulated outputoscillation to produce the outbound RF signal 104. If the outboundsymbol stream 102 includes amplitude modulation information 142, theamplifier module 122 modulates the frequency modulated outputoscillation in accordance with the amplitude modulation information 142to produce the outbound RF signal 104.

FIG. 7 is a schematic block diagram of an embodiment of a loop filter128 that includes the pole circuit 134 and the zero circuit 136. Thezero circuit 136 includes an on-chip resistor 152, a metal oxidesemiconductor (MOS) capacitor 150, and a conversion module 178. The zerocircuit 136 yields a zero at a frequency corresponding to the product ofthe on-chip resistor 152 and the MOS capacitor 150. The off-chipcalibration resistor 138 is coupled to a resistor (R) calibrationcircuit 176, which is coupled to the conversion module 178 to facilitatethe compensation of the zero circuit 136. An embodiment of the zerocircuit 134 will be described in greater detail with reference to FIG.8.

The pole circuit 134 includes a first pole capacitor (C0), a resistor(pole R), and a second capacitor (C1). The first pole capacitor, whichmay be a metal capacitor, provides a first pole at DC. The secondcapacitor, which may be a metal capacitor, and the second resistorprovide a second pole at a frequency corresponding to the product of thetwo components. To ensure that the second pole is at the desiredfrequency, the RC calibration circuit 160 calibrates the second resistorand/or the second capacitor. In such an embodiment, the loop filter 128establishes the bandwidth for the PLL 120, which is much greater thanthe inverse of a frequency response of the zero circuit.

FIG. 8 is a schematic block diagram of an embodiment of the zero circuit136 that includes the on-chip resistor 152, the MOS capacitor 150, andthe conversion module 178. The R calibration circuit 176 and theoff-chip calibration resistor 138 are coupled to the conversion module178. The MOS capacitor 150 includes a base MOS capacitor 172 and aplurality of gated MOS capacitors 174.

To calibrate the zero circuit 136, and in particular, the MOS capacitor150, the R calibration circuit 176 is coupled to the off-chipcalibration resistor 138 to produce a resistor variation indication 180.For example, the off-chip calibration resistor 138 may be a highprecision resistor (e.g., tolerance of 1% or less) that is coupled toreceive a reference current and thereby produce a voltage. The samereference current is provided to an on-chip resistor, which may be theon-chip resistor 152 or an on-chip resistor that has similar propertiesto the on-chip resistor 152, to produce a second voltage. The Rcalibration circuit compares the two voltages to determine the resistorvariation indication 180.

The conversion module 178, which may be a look up table, a voltage todigital signal mapping function, etc., converts the resistor variationindication 180 into a MOS capacitor adjust signal 182. The MOS capacitoradjust signal 182 enables at least one of the plurality of gated MOScapacitors 174 such that the MOS capacitor 150 compensates for the errorof the on-chip resistor 152 to establish the zero at the desiredfrequency.

FIG. 9 is a schematic block diagram of an embodiment of a PLL 120 thatincludes the phase detector 124, the charge pump 126, a loop filter 128,the controlled oscillator 130, and the feedback divider 132. The loopfilter 128 includes a first resistor-capacitor (RC) circuit 190 and asecond RC circuit 192. In this embodiment, the first resistor-capacitorcircuit 190 is calibrated using a first calibration technique 194 andthe second resistor-capacitor circuit 192 is calibrated using a secondcalibration technique 196. The loop filter 128 of this embodiment willbe described in greater detail with reference to FIG. 10.

FIG. 10 is a schematic block diagram of another embodiment of a loopfilter 128 that includes the first RC circuit 190, the second RC circuit192, a resistor (R) calibration circuit 200, the conversion module 178,and an RC calibration circuit 160. The first RC circuit 190 includes theon-chip resistor 152 and the MOS capacitor 150 to provide a zero at adesired frequency. The second RC circuit 192 includes the first polecapacitor, which may be a metal capacitor, to provide a first pole atDC. The second RC circuit 192 also includes a second capacitor, whichmay be a metal capacitor, and the second resistor provide a second poleat a frequency corresponding to the product of the two components. Toensure that the second pole is at the desired frequency, the RCcalibration circuit 160 calibrates the second resistor and/or the secondcapacitor.

In an embodiment, the MOS capacitor 150 may include a base metal oxidesemiconductor (MOS) capacitor and a plurality of gated MOS capacitorscoupled in parallel with the base MOS capacitor. In this embodiment, theR calibration circuit 200 may include an on-chip calibration resistorand is coupled to an off-chip calibration resistor to produce a resistorvariation indication of the on-chip resistor. The conversion module 178is coupled to convert the resistor variation indication into a MOScapacitor adjust signal, wherein the MOS capacitor adjust signal enablesat least one of the plurality of gated MOS capacitors.

As may be used herein, the terms “substantially” and “approximately”provides an industry-accepted tolerance for its corresponding termand/or relativity between items. Such an industry-accepted toleranceranges from less than one percent to fifty percent and corresponds to,but is not limited to, component values, integrated circuit processvariations, temperature variations, rise and fall times, and/or thermalnoise. Such relativity between items ranges from a difference of a fewpercent to magnitude differences. As may also be used herein, theterm(s) “coupled to” and/or “coupling” and/or includes direct couplingbetween items and/or indirect coupling between items via an interveningitem (e.g., an item includes, but is not limited to, a component, anelement, a circuit, and/or a module) where, for indirect coupling, theintervening item does not modify the information of a signal but mayadjust its current level, voltage level, and/or power level. As mayfurther be used herein, inferred coupling (i.e., where one element iscoupled to another element by inference) includes direct and indirectcoupling between two items in the same manner as “coupled to”. As mayeven further be used herein, the term “operable to” indicates that anitem includes one or more of power connections, input(s), output(s),etc., to perform one or more its corresponding functions and may furtherinclude inferred coupling to one or more other items. As may stillfurther be used herein, the term “associated with”, includes directand/or indirect coupling of separate items and/or one item beingembedded within another item. As may be used herein, the term “comparesfavorably”, indicates that a comparison between two or more items,signals, etc., provides a desired relationship. For example, when thedesired relationship is that signal 1 has a greater magnitude thansignal 2, a favorable comparison may be achieved when the magnitude ofsignal 1 is greater than that of signal 2 or when the magnitude ofsignal 2 is less than that of signal 1.

While the transistors in the above described figure(s) is/are shown asfield effect transistors (FETs), as one of ordinary skill in the artwill appreciate, the transistors may be implemented using any type oftransistor structure including, but not limited to, bipolar, metal oxidesemiconductor field effect transistors (MOSFET), N-well transistors,P-well transistors, enhancement mode, depletion mode, and zero voltagethreshold (VT) transistors.

The present invention has also been described above with the aid ofmethod steps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid offunctional building blocks illustrating the performance of certainsignificant functions. The boundaries of these functional buildingblocks have been arbitrarily defined for convenience of description.Alternate boundaries could be defined as long as the certain significantfunctions are appropriately performed. Similarly, flow diagram blocksmay also have been arbitrarily defined herein to illustrate certainsignificant functionality. To the extent used, the flow diagram blockboundaries and sequence could have been defined otherwise and stillperform the certain significant functionality. Such alternatedefinitions of both functional building blocks and flow diagram blocksand sequences are thus within the scope and spirit of the claimedinvention. One of average skill in the art will also recognize that thefunctional building blocks, and other illustrative blocks, modules andcomponents herein, can be implemented as illustrated or by discretecomponents, application specific integrated circuits, processorsexecuting appropriate software and the like or any combination thereof.

1. A phase locked loop (PLL) comprises: a phase detector coupled toproduce a difference signal based on a difference between phase of areference oscillation and phase of a feedback oscillation; a charge pumpcoupled to convert the difference signal into an up-signal or a downsignal; a loop filter coupled to filter the up signal or the down signalto produce a control signal; a controlled oscillator coupled to generatean output oscillation based on the control signal; and a feedbackdivider coupled to generate the feedback oscillation from the outputoscillation based on a divider value, wherein the loop filter includes:a first resistor-capacitor circuit, having a first resistor, a firstcapacitor coupled in series with the first resistor to provide a zero ofthe loop filter, the first capacitor comprises: a base metal oxidesemiconductor (MOS) capacitor; and a plurality of gated MOS capacitorscoupled in parallel with the base MOS capacitor; and a secondresistor-capacitor circuit, wherein the first resistor-capacitor circuitis calibrated using a first calibration technique and the secondresistor-capacitor circuit is calibrated using a second calibrationtechnique.
 2. The PLL of claim 1 comprises: a resistor calibrationcircuit to perform the first calibration technique.
 3. The PLL of claim2, wherein the resistor calibration circuit comprises: an off-chipcalibration resistor; a resistor calibration circuit coupled to theoff-chip calibration resistor to produce an on-chip resistor variationindication; and a conversion module coupled to convert the resistorvariation indication into a MOS capacitor adjust signal, wherein the MOScapacitor adjust signal enables at least one of the plurality of gatedMOS capacitors.
 4. The PLL of claim 1, wherein the secondresistor-capacitor circuit comprises: a pole capacitor to provide afirst pole; a second resistor; and a second capacitor coupled to thesecond resistor to provide a second pole.
 5. The PLL of claim 4comprises: a resistor-capacitor calibration circuit to perform thesecond calibration technique.
 6. The PLL of claim 1 comprises: a loopbandwidth that is much greater than an inverse of a frequency responseof the first resistor-capacitor circuit.
 7. An on-chip phase locked loop(PLL) comprises: a phase detector coupled to produce a difference signalbased on a difference between phase of a reference oscillation and phaseof a feedback oscillation; a charge pump coupled to convert thedifference signal into an up-signal or a down signal; a loop filtercoupled to filter the up signal or the down signal to produce a controlsignal, wherein the loop filter includes: a pole circuit that includesat least one resistor and at least one capacitor; a zero circuit thatincludes at least one resistor and at least one metal oxidesemiconductor (MOS) capacitor: wherein the pole circuit and zero circuitprovide a desired frequency response for the PLL; wherein the MOScapacitor comprises: a base metal oxide semiconductor (MOS) capacitor;and a plurality of gated MOS capacitors coupled in parallel with thebase MOS capacitor; and an off-chip calibration resistor operable tofacilitate compensation of the zero circuit; a controlled oscillatorcoupled to generate an output oscillation based on the control signal;and a feedback divider coupled to generate the feedback oscillation fromthe output oscillation based on a divider value.
 8. The on-chip PLL ofclaim 7, wherein the pole circuit comprises: a pole capacitor to providea first pole; a second resistor; and a second capacitor coupled to thesecond resistor to provide a second pole.
 9. The on-chip PLL of claim 8comprises: a resistor-capacitor calibration circuit to calibrate thesecond resistor and the second capacitor to provide the second pole at adesired pole location.
 10. The on-chip PLL of claim 7 comprises: a loopbandwidth that is much greater than an inverse of a frequency responseof the zero circuit.
 11. An on-chip phase locked loop (PLL) comprises: aphase detector coupled to produce a difference signal based on adifference between phase of a reference oscillation and phase of afeedback oscillation; a charge pump coupled to convert the differencesignal into an up-signal or a down signal; a loop filter coupled tofilter the up signal or the down signal to produce a control signal,wherein the loop filter includes: a pole circuit that includes at leastone resistor and at least one capacitor; a zero circuit that includes atleast one resistor and at least one metal oxide semiconductor (MOS)capacitor, wherein the pole circuit and zero circuit provide a desiredfrequency response for the PLL; and an off-chip calibration resistoroperable to facilitate compensation of the zero circuit; a controlledoscillator coupled to generate an output oscillation based on thecontrol signal; a feedback divider coupled to generate the feedbackoscillation from the output oscillation based on a divider value; aresistor calibration circuit coupled to the off-chip calibrationresistor to produce an on-chip resistor variation indication; and aconversion module coupled to convert the resistor variation indicationinto a MOS capacitor adjust signal, wherein the MOS capacitor adjustsignal enables at least one of the plurality of gated MOS capacitors.